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Q： After changing the system clock of MCU from the default 8MHz to 48MHz, what is the reason that the program runs away and cannot be debugged?A： The internal FLASH memory of CW32F030 supports the fastest 24MHz operation clock. When the configured HCLK frequency is greater than 24MHz, the number of wait HCLK cycles to be inserted should be configured through the WAIT bit field of FLASH_CR2 in the FLASH control register. For greater than 24MHz and less than or equal to 48MHz, 1 wait cycle needs to be inserted; for greater than 48MHz, 2 wait cycles need to be inserted.
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Q： The SWD port is set to a normal GPIO, which makes it impossible to connect to the emulator.A： After switching the SWD port to normal GPIO port, the SWD function is not available and the chip cannot connect to the emulator, resulting in no more program burning. If necessary, it is recommended to switch the SWD port to normal GPIO port after power-on reset and delay for some time.
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Q： Can the state of GPIOs be maintained after the CW32F030 enters hibernation mode?A： After the CW32F030 enters the hibernation mode, the state of the GPIOs is automatically maintained without user software involvement.
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Q： What is the lowest power consumption the CW32F030 can do?A： When the CW32F030 enters deep sleep mode, the CPU stops running, the high-speed clocks (HSE, HSIOSC) are automatically turned off, and only the low-speed clocks and a small number of peripherals are kept running (e.g., RTC, IWDT, LVD, GPIO, VC, UART, and AWT, etc.), and the power consumption of the MCU will be greatly reduced. If all peripherals are turned off before entering deep sleep mode, the power consumption can be reduced to less than 20uA after entering deep sleep mode.
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Q： The CW32F030 is a 32-bit MCU, why doesn't it provide a 32-bit timer?A： CW32F030 provides rich timer resources, there are one advanced timer, four general-purpose timers and three basic timers. Although the timers are 16-bit, each timer can be used in cascade, and can be cobbled together to be used as a 32-bit or higher-bit timer, which is very flexible.
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Q： What is the maximum clock frequency for SPI?A： The maximum clock frequency of SPI is 12MHz. although the SCK frequency of SPI can be configured as PCLK/2 in host mode, the actual communication rate cannot exceed 12MHz due to the limitation of the delay of GPIO.
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